In recent years, an increase of electric power consumption caused by leakage currents of transistors has been problematic as a degree of integration of semiconductors increases. An arrangement in which a memory element and a logic element have been separated from each other results in data transfer delay and increased electric power consumption of wires for data transfer, both of which have also been problematic.
As one of methods for solving those problems, Patent Literature 1 has proposed an integrated circuit using a nonvolatile logic gate in which a memory element and a logic element have been integrated with each other. This integrated circuit is characterized in that data are not eliminated even if a power source is turned off because data are stored by a plurality of nonvolatile resistive elements. Therefore, the integrated circuit can dispense with a power source for holding data during an inoperative period. Accordingly, electric power consumption by a leakage current during an inoperative period can be reduced. Additionally, since the memory element and the logic element are arranged close to each other, the integrated circuit is expected to be operated with less wiring delay and less electric power consumption.
FIG. 1 shows an example of an arrangement of a nonvolatile logic gate that can be used for the aforementioned integrated circuit. The illustrated nonvolatile logic gate includes an NMOS logic circuit, nonvolatile resistive elements R1 and R2 and a through current control circuit for storing complementary data as resistance values, a sense circuit, and a writing part used for writing or rewriting data of the nonvolatile resistive elements. Furthermore, the sense circuit includes PMOS transistors P1 and P2 for latching output data and two PMOS transistors P3 and P4 for precharge. The sense circuit is connected to the NMOS logic circuit. Each of the illustrated nonvolatile resistive elements R1 and R2 has a first end connected to the NMOS logic circuit and a second end connected to the through current control circuit.
Next, specific connections of the components of the nonvolatile logic gate shown in FIG. 1 will be described. A gate of the PMOS transistor P1 is connected to a drain of the PMOS transistor P2, a drain of the PMOS transistor P4, and the NMOS logic circuit, and is also connected to a data output terminal for outputting an output signal /Dout. Meanwhile, a gate of the PMOS transistor P2 is connected to a drain of the PMOS transistor P1, a drain of the PMOS transistor P3, and the NMOS logic circuit, and is also connected to a data output terminal for outputting an output signal Dout. Gates of the PMOS transistors P3 and P4 are supplied with a clock signal CLK. Each of sources of the PMOS transistors P1, P2, P3, and P4 is connected to a power source voltage Vdd.
For example, a magnetic tunnel junction (MTJ) element using magnetoresistance effects may be used for the nonvolatile resistive elements R1 and R2 shown in FIG. 1. Here, an MTJ element has a ferromagnetic layer (free layer) variable in a direction of magnetization, a ferromagnetic layer (fixed layer) fixed in a direction of magnetization, and an insulator layer formed between the free layer and the fixed layer. When a current is supplied in a direction perpendicular to the film surface of such an MTJ element, the resistance value of the MTJ element varies depending upon the magnetization directions of the free layer and the fixed layer. The resistance value of the MTJ element decreases when the magnetization of the free layer and the magnetization of the fixed layer are parallel to each other, whereas the resistance value of the MTJ element increases when the magnetization of the free layer and the magnetization of the fixed layer are opposite to each other.
The MTJ element uses those characteristics to store data corresponding to the magnitude of the resistance value, i.e., the direction of the free layer. For example, a low-resistance state is made to correspond to data “0” while a high-resistance state is made to correspond to data “1”. The nonvolatile logic gate uses data of this MTJ element for a logical operation.
Methods of writing data into an MTJ element include a magnetic field writing method of controlling a magnetization direction of a free layer by the use of a current magnetic field and a spin torque writing method of controlling a magnetization direction of a free layer by the use of a spin torque effect.
The nonvolatile logic gate shown in FIG. 1 performs a logical operation by the use of data stored in the nonvolatile resistive elements R1 and R2. Specifically, the nonvolatile logic gate performs a calculation between data stored in the nonvolatile resistive elements R1 and R2 and an input data Din externally inputted into the NMOS logic circuit, and outputs complementary outputs Dout and /Dout. A designer can determine what operation is performed by the nonvolatile logic gate, and can properly design the NMOS logic circuit for that purpose.
Now a configuration of the through current control circuit connected to the nonvolatile resistive elements R1 and R2 will be described with reference to FIGS. 2(a) and 2(b). The through current control circuit shown in FIG. 2(a) has an NMOS transistor N1. A drain of the NMOS transistor N1 is connected to an end of each of the nonvolatile resistive elements R1 and R2. A source of the NMOS transistor N1 is grounded, and a gate of the NMOS transistor N1 is supplied with a clock signal CLK.
Meanwhile, the through current control circuit shown in FIG. 2(b) has two NMOS transistors N1 and N2 and a capacitor C1 having a first end being grounded and a second end connected to a common junction of the NMOS transistors N1 and N2. Furthermore, a drain of the NMOS transistor N1 is connected to an end of each of the nonvolatile resistive elements R1 and R2, and a source of the NMOS transistor N1 is connected to a drain of the NMOS transistor N2 and the end of the capacitor C1. A gate of the NMOS transistor N1 is supplied with a clock signal CLK. A source of the NMOS transistor N2 is grounded, and a gate of the NMOS transistor N2 is supplied with an inversed clock signal /CLK.
The through current control circuits shown in FIGS. 2(a) and 2(b) differ from each other in existence or in non-existence of a through current flowing during a logical operation. In the case of the through current control circuit shown in FIG. 2(a), a current steadily flows through the nonvolatile resistive elements R1 and R2 and the NMOS transistor N1 when the clock signal CLK is at a high level. On the other hand, in the case of the through current control circuit shown in FIG. 2(b), a current flows through the nonvolatile resistive elements R1 and R2 and the NMOS transistor N1 only during the charging of the capacitor C1 when the clock signal CLK is at a high level. Therefore, less steady current flows in the circuit shown in FIG. 2(b) than in the circuit shown in FIG. 2(a). Accordingly, the through current control circuit shown in FIG. 2(b) can reduce electric power consumption during an operation.
FIG. 2(c) shows an example of an NMOS logic circuit forming a nonvolatile logic gate. This exemplary circuit illustrates an NMOS logic circuit (SUM circuit) for performing an addition or a sum operation. The illustrated NMOS logic circuit has eight NMOS transistors N3, N4, N5, N6, N7, N8, N9, and N10. Complementary input signals A and /A and C and /C are inputted as data input signals Din into gates of the NMOS transistors N3 to N10. A current path is formed in each of the NMOS logic circuits depending upon the corresponding input signal. An end of the nonvolatile resistive element R1 in the illustrated circuit configuration is electrically connected to the NMOS logic circuit on a side of outputting a data output Dout. An end of the nonvolatile resistive element R2 is electrically connected to the NMOS logic circuit on a side of outputting a data output /Dout. A difference of current values flowing through those two current paths is used to determine output voltages as data outputs Dout and /Dout, i.e., logical operation results (output results).
A nonvolatile logic gate formed by a combination of the components illustrated in FIGS. 1, 2(b), and 2(c) operates in the following manner. The illustrated nonvolatile logic gate has a precharge period and an evaluation period. Such an operation of the nonvolatile logic gate is a particular operation that differs from an operation of a general static CMOS circuit.
First, there is defined a precharge period during which a clock signal CLK is at a low level. During the precharge period, the NMOS transistor N1 of the through current control circuit (FIG. 2(b)) is turned off, and the PMOS transistors P3 and P4 of the sense circuit (FIG. 1) precharge the outputs Dout and /Dout into a power source voltage Vdd. Furthermore, at that timing, the NMOS transistor N2 (FIG. 2(b)) of the through current control circuit discharges charges accumulated in the capacitor C1.
Meanwhile, there is defined an evaluation period during which the clock signal CLK is at a high level. During the evaluation period, the NMOS transistor N1 of the through current control circuit (FIG. 2(b)) is turned on, the NMOS transistor N2 is turned off, and the precharge PMOS transistors P3 and P4 of the sense circuit (FIG. 1) is turned off.
The charges accumulated in capacitors (not shown) during the precharge flow into the capacitor C1 of the through current control circuit via the two current paths formed within the NMOS logic circuit and the nonvolatile resistive elements R1 and R2, which have stored the complementary resistance values. The currents flow through the nonvolatile resistive elements R1 and R2 depend upon the resistance values of the nonvolatile resistive elements R1 and R2. Therefore, a potential difference is produced between Dout and /Dout, which are complementary outputs. The potential difference is amplified by the PMOS transistors P1 and P2, and then complementary data output Dout and /Dout are outputted. It should be noted that, in this nonvolatile logic gate, the input signals A, /A, C, and /C should be unchanged during the evaluation period, during which the clock signal CLK is at a high level. In this manner, the nonvolatile logic gate has an operation function and a latch function.